Indicates the implemented SVC instructions:
0x1 The SVC instruction.
SIMD, [7:4]
Indicates the implemented Single Instruction Multiple Data (SIMD) instructions.
0x3 • The SSAT and USAT instructions, and the Q bit in the PSRs.
• The PKHBT, PKHTB, QADD16, QADD8, QASX, QSUB16, QSUB8, QSAX, SADD16, SADD8,
SASX, SEL, SHADD16, SHADD8, SHASX, SHSUB16, SHSUB8, SHSAX, SSAT16, SSUB16,
SSUB8, SSAX, SXTAB16, SXTB16, UADD16, UADD8, UASX, UHADD16, UHADD8, UHASX,
UHSUB16, UHSUB8, UHSAX, UQADD16, UQADD8, UQASX, UQSUB16, UQSUB8, UQSAX,
USAD8, USADA8, USAT16, USUB16, USUB8, USAX, UXTAB16, UXTB16 instructions, and
the GE[3:0] bits in the PSRs.
Saturate, [3:0]
Indicates the implemented Saturate instructions:
0x1 The QADD, QDADD, QDSUB, QSUB and the Q bit in the PSRs.
To access the ID_ISAR3_EL1:
MRS <Xt>, ID_ISAR3_EL1 ; Read ID_ISAR3_EL1 into Xt
Register access is encoded as follows:
Table B2-52 ID_ISAR3_EL1 access encoding
op0 op1 CRn CRm op2
11 000 0000 0010 011
B2 AArch64 system registers
B2.60 AArch32 Instruction Set Attribute Register 3, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-462
Non-Confidential
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