0x1 Security implemented. This includes support for Monitor mode and the SMC
instruction.
ProgMod, [3:0]
Indicates support for the standard programmers model for Armv4 and later.
Model must support User, FIQ, IRQ, Supervisor, Abort, Undefined, and System modes:
0x1 Supported.
To access the ID_PFR1_EL1:
MRS <Xt>, ID_PFR1_EL1 ; Read ID_PFR1_EL1 into Xt
Register access is encoded as follows:
Table B2-60 ID_PFR1_EL1 access encoding
op0 op1 CRn CRm op2
1111 000 0000 0001 001
B2 AArch64 system registers
B2.68 AArch32 Processor Feature Register 1, EL1
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reserved.
B2-478
Non-Confidential