ARM Cortex-A35 User Manual

Table B2-61 Encodings of LL bits associated with the MMU fault
Bits Meaning
0b00
Reserved
0b01
Level 1
0b10
Level 2
0b11
Level 3
If a Data Abort exception is generated by an instruction cache maintenance operation when the Long-
descriptor translation table format is selected, the fault is reported as a Cache Maintenance fault in the
DFSR or HSR with the appropriate Fault Status code. For such exceptions reported in the DFSR, the
corresponding IFSR32_EL2 is UNKNOWN.
To access the IFSR32_EL2:
MRS <Xt>, IFSR32_EL2 ; Read IFSR32_EL2 into Xt
MSR IFSR32_EL2, <Xt> ; Write Xt to IFSR32_EL2
Register access is encoded as follows:
Table B2-62 IFSR32_EL2 access encoding
op0 op1 CRn CRm op2
11 000 0101 0000 001
B2 AArch64 system registers
B2.71 IFSR32_EL2 with Long-descriptor translation table format
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English