[6:1]
Reserved, RES0.
F, [0]
Pass/Fail bit. Indicates whether the conversion completed successfully. This value is:
0 Virtual Address to Physical Address conversion completed successfully.
The following figure shows the PAR_EL1 bit assignments when the Virtual Address to Physical Address
conversion is aborted.
RES0
63
0
S FST
10 9 8 7 6 1
F
1112
RES1
RES0 PTW
RES0
Figure B2-56 PAR_EL1 fail bit assignments
The following list shows the PAR_EL1 bit assignments when the Virtual Address to Physical Address
conversion is aborted.
[63:12]
Reserved, RES0.
[11]
Reserved, RES1.
[10]
Reserved, RES0.
S, [9]
Stage of fault. Indicates the state where the translation aborted. The possible values are:
0 Translation aborted because of a fault in stage 1 translation.
1 Translation aborted because of a fault in stage 2 translation.
PTW, [8]
Indicates a stage 2 fault during a stage 1 table walk. The possible values are:
0 No stage 2 fault during a stage 1 table walk.
1 Translation aborted because of a stage 2 fault during a stage 1 table walk.
[7]
Reserved, RES0.
FST, [6:1]
Fault status code, as the Data Abort ESR encoding shows it. See the Arm
®
Architecture
Reference Manual Armv8, for Armv8-A architecture profile for more information.
F, [0]
Pass/Fail bit. Indicates whether the conversion completed successfully. This value is:
1 Virtual Address to Physical Address conversion aborted.
To access the PAR_EL1:
MRS <Xt>, PAR_EL1 ; Read EL1 Physical Address Register
MSR PAR_EL1, <Xt> ; Write EL1 Physical Address Register
Register access is encoded as follows:
B2 AArch64 system registers
B2.85 Physical Address Register, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-516
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