Chapter A3 Clocks, Resets, and Input Synchronization
A3.1 Clocks ......................................................... ......................................................... A3-50
A3.2 Input synchronization ............................................................................................ A3-51
A3.3 Resets ......................................................... ......................................................... A3-52
Chapter A4 Power Management
A4.1 Power domains .................................................. .................................................. A4-58
A4.2 Power modes ........................................................................................................ A4-61
A4.3 Core Wait for Interrupt ............................................. ............................................. A4-62
A4.4 Core Wait for Event ............................................... ............................................... A4-63
A4.5 L2 Wait for Interrupt .............................................................................................. A4-64
A4.6 Powering down an individual core .................................... .................................... A4-65
A4.7 Powering up an individual core ...................................... ...................................... A4-66
A4.8 Powering down the processor without system driven L2 flush .............................. A4-67
A4.9 Powering up the processor without system driven L2 flush .................................. A4-68
A4.10 Powering down the processor with system driven L2 flush ................. ................. A4-69
A4.11 Powering up the processor with system driven L2 flush ................... ................... A4-70
A4.12 Entering Dormant mode ........................................................................................ A4-71
A4.13 Exiting Dormant mode ............................................. ............................................. A4-72
A4.14 Event communication using WFE or SEV .............................. .............................. A4-73
A4.15 Communication to the Power Management Controller .................... .................... A4-74
A4.16 STANDBYWFI[3:0] and STANDBYWFIL2 signals ........................ ........................ A4-75
A4.17 Q-channel .............................................................................................................. A4-76
Chapter A5 Cache Behavior and Cache Protection
A5.1 Cached memory types .......................................................................................... A5-78
A5.2 Coherency between data caches with the MOESI protocol .................................. A5-79
A5.3 Cache misses, unexpected cache hits, and speculative fetches .......................... A5-80
A5.4 Disabling a cache .................................................................................................. A5-81
A5.5 Invalidating or cleaning a cache ............................................................................ A5-82
A5.6 About read allocate mode .......................................... .......................................... A5-83
A5.7 About cache protection ............................................ ............................................ A5-84
A5.8 Error reporting ................................................... ................................................... A5-86
A5.9 Error injection ........................................................................................................ A5-87
Chapter A6 L1 Memory System
A6.1 About the L1 memory system ....................................... ....................................... A6-90
A6.2 TLB Organization .................................................................................................. A6-91
A6.3 Program flow prediction ........................................................................................ A6-92
A6.4 About the internal exclusive monitor .................................. .................................. A6-93
A6.5 About data prefetching .......................................................................................... A6-95
Chapter A7 L2 Memory System
A7.1 About the L2 memory system ....................................... ....................................... A7-98
A7.2 Snoop and maintenance requests ...................................................................... A7-100
A7.3 Support for memory types ......................................... ......................................... A7-101
A7.4 Memory type information exported from the processor ................... ................... A7-102
A7.5 Handling of external aborts ........................................ ........................................ A7-103
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