ARM Cortex-A35

Table C5-7 MOESI state
Tag RAM partial MOESI bits Dirty RAM partial MOESI bits MOESI state
00 x Invalid (I)
01 0 SharedClean (S)
1 SharedDirty (O)
1x 0 UniqueClean (E)
1 UniqueDirty (M)
Related information
A5.2 Coherency between data caches with the MOESI protocol on page A5-79
C5 Direct access to internal memory
C5.3 Encoding for tag and data in the L1 data cache
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