ARM Cortex-A35

To access the PMCEID1:
MRC p15,0,<Rt>,c9,c12,7 ; Read PMCEID1 into Rt
The PMCEID1 can be accessed through the external debug interface, offset 0xE24.
C10 PMU registers
C10.4 Performance Monitors Common Event Identification Register 1
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C10-701
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