Number of events supported in the trace, minus 1:
0b11 Four events supported.
RETSTACK, [9]
Return stack support:
1 Return stack implemented.
[8]
Reserved, RES0.
TRCCCI, [7]
Support for cycle counting in the instruction trace:
1 Cycle counting in the instruction trace is implemented.
TRCCOND, [6]
Support for conditional instruction tracing:
0 Conditional instruction tracing is not supported.
TRCBB, [5]
Support for branch broadcast tracing:
1 Branch broadcast tracing is implemented.
TRCDATA, [4:3]
Conditional tracing field:
0b00 Tracing of data addresses and data values is not implemented.
INSTP0, [2:1]
P0 tracing support field:
0b00 Tracing of load and store instructions as P0 elements is not supported.
[0]
Reserved, RES1.
The TRCIDR0 can be accessed through the external debug interface, offset 0x1E0.
C11 ETM registers
C11.32 ID Register 0
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C11-774
Non-Confidential
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