SYNCPR, [25]
Indicates whether there is a fixed synchronization period:
0 TRCSYNCPR is read-write so software can change the synchronization period.
TRCERR, [24]
Indicates whether TRCVICTLR.TRCERR is implemented:
1 TRCVICTLR.TRCERR is implemented.
EXLEVEL_NS, [23:20]
Each bit controls whether instruction tracing in Non-secure state is implemented for the
corresponding exception level:
0b0111 Instruction tracing is implemented for Non-secure EL0, EL1 and EL2 exception levels.
EXLEVEL_S, [19:16]
Each bit controls whether instruction tracing in Secure state is implemented for the
corresponding exception level:
0b1011 Instruction tracing is implemented for Secure EL0, EL1 and EL3 exception levels.
[15:12]
Reserved, RES0.
CCITMIN, [11:0]
The minimum value that can be programmed in TRCCCCTLR.THRESHOLD:
0x004 Instruction trace cycle counting minimum threshold is 4.
The TRCIDR3 can be accessed through the external debug interface, offset 0x1EC.
C11 ETM registers
C11.35 ID Register 3
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C11-779
Non-Confidential
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