ARM Cortex-A35 User Manual

Table A10-6 CHI transactions (continued)
Transaction Operation
WriteBackFull Evictions of dirty lines from the L1 or L2 cache.
WriteBackPtl Not used.
WriteCleanFull Evictions of dirty lines from the L2 cache, when the line is still present in an L1 cache. Some cache maintenance
instructions.
WriteCleanPtl Not used.
WriteEvictFull Evictions of unique clean lines, when configured in the L2ACTLR.
Evict Evictions of clean lines, when configured in the L2ACTLR.
External memory accesses generate the following transactions in an implementation configured with a
CHI master interface.
Table A10-7 CHI transactions
Attributes CHI transaction
Memory type Shareability SnpAttr Load Store Load
exclusive
Store exclusive
Device - Non-
snoopable
ReadNoSnp WriteNoSnp
ReadNoSnp and
Excl set to HIGH
WriteNoSnp and
Excl set to HIGH
Normal, inner Non-
cacheable, outer Non-
cacheable
Non-shared Non-
snoopable
ReadNoSnp WriteNoSnp
ReadNoSnp and
Excl set to HIGH
WriteNoSnp and
Excl set to HIGH
Inner-shared
Outer-shared
Normal, inner Non-
cacheable, outer Write-
Back or Write-
Through, or Normal,
inner Write-Through,
outer Write-Back,
Write-Through or Non-
cacheable, or Normal
inner Write-Back outer
Non-cacheable or
Write-Through
Non-shared Non-
snoopable
ReadNoSnp WriteNoSnp
ReadNoSnp ReadNoSnp
Inner-shared Non-
snoopable
ReadNoSnp WriteNoSnp ReadNoSnp with
Excl set to HIGH
WriteNoSnp with
Excl set to HIGH
Outer-shared Non-
snoopable
A10 CHI Master Interface
A10.5 CHI transactions
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A10-132
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English