ARM Cortex-A35 User Manual

Table A3-1 Valid reset combinations
Reset combination Signals Value Description
Cluster cold reset
nCPUPORESET[CN:0]
nCORERESET[CN:0]
nPRESETDBG
nL2RESET
nMBISTRESET
all = 0
all = X
0
0
1
All logic is held in reset.
nCORERESET can be asserted, but is not required.
Cluster cold reset with debug
active
nCPUPORESET[CN:0]
nCORERESET[CN:0]
nPRESETDBG
nL2RESET
nMBISTRESET
all = 0
all = X
1
0
1
All cores are held in reset so they can be powered up. The L2 is
held in reset, but must remain powered up. This enables external
debug over power down for the cluster.
nCORERESET can be asserted, but is not required.
Individual core cold reset
with debug active
nCPUPORESET[CN:0]
nCORERESET[CN:0]
nPRESETDBG
nL2RESET
nMBISTRESET
[n] = 0
[n] = X
1
1
1
Individual core is held in reset, so that the core can be powered up.
This enables external debug over power down for the core that is
held in reset.
nCORERESET can be asserted, but is not required.
Individual core warm reset
with trace and debug active
nCPUPORESET[CN:0]
nCORERESET[CN:0]
nPRESETDBG
nL2RESET
nMBISTRESET
[n] = 1
[n] = 0
1
1
1
Individual core is held in reset.
Debug logic reset
nCPUPORESET[CN:0]
nCORERESET[CN:0]
nPRESETDBG
nL2RESET
nMBISTRESET
all = 1
all = 1
0
1
1
Cluster debug logic is held in reset.
A3 Clocks, Resets, and Input Synchronization
A3.3 Resets
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English