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ARM Cortex-A35 User Manual

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Table C10-7 Memory-mapped PMU register summary (continued)
Offset Name Type Description
0xFE4
PMPIDR1 RO C10.13 Performance Monitors Peripheral Identification Register 1
on page C10-721
0xFE8
PMPIDR2 RO C10.14 Performance Monitors Peripheral Identification Register 2
on page C10-722
0xFEC
PMPIDR3 RO C10.15 Performance Monitors Peripheral Identification Register 3
on page C10-723
0xFF0
PMCIDR0 RO C10.19 Performance Monitors Component Identification Register 0
on page C10-727
0xFF4
PMCIDR1 RO C10.20 Performance Monitors Component Identification Register 1
on page C10-728
0xFF8
PMCIDR2 RO C10.21 Performance Monitors Component Identification Register 2
on page C10-729
0xFFC
PMCIDR3 RO C10.22 Performance Monitors Component Identification Register 3
on page C10-730
C10 PMU registers
C10.9 Memory-mapped PMU register summary
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C10-716
Non-Confidential

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ARM Cortex-A35 Specifications

General IconGeneral
BrandARM
ModelCortex-A35
CategoryComputer Hardware
LanguageEnglish

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