ARM Cortex-A35 User Manual

Table A-42 Debug signals (continued)
Signal Direction Description
SPIDEN[CN:0] Input
Secure privileged invasive debug enable:
0
Not enabled.
1
Enabled.
SPNIDEN[CN:0] Input
Secure privileged non-invasive debug enable:
0
Not enabled.
1
Enabled.
DBGRSTREQ[CN:0] Output Warm reset request.
DBGNOPWRDWN[CN:0] Output
Request not to power down the core:
0
Do not request that the core stays powered up.
1
Request that the core stays powered up.
DBGPWRUPREQ[CN:0] Output
Core power- up request:
0
Do not request that the core is powered up.
1
Request that the core is powered up.
DBGPWRDUP[CN:0] Input
Core powered up:
0
Core is powered down.
1
Core is powered up.
DBGL1RSTDISABLE Input
Disable the automatic invalidation of the L1 data cache at processor reset:
0
Enable automatic invalidation of L1 data cache on reset.
1
Disable automatic invalidation of L1 data cache on reset.
This signal is sampled only during processor reset.
Related information
Chapter C1 Debug on page C1-575
Chapter C6 AArch32 debug registers on page C6-619
Chapter C7 AArch64 debug registers on page C7-633
Chapter C8 Memory-mapped debug registers on page C8-643
Chapter C9 ROM table on page C9-669
A Signal Descriptions
A.14 Debug signals
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English