ARM Cortex-A35 User Manual

Table B-1 Armv8 Debug UNPREDICTABLE behaviors (continued)
Scenario Behavior
Address match breakpoint with
DBGBCRn_EL1.BAS=0000
The processor implements the following option:
• As if disabled.
DBGWCRn_EL1.BAS specifies a non-
contiguous set of bytes within a double-word
The processor implements the following option:
• A Watchpoint debug event is generated for each byte.
A32 HLT instruction with condition code not
AL
The processor implements the following option:
• Executed unconditionally.
Execute instruction at a given EL when the
corresponding EDECCR bit is 1 and Halting
is allowed
The processor behaves as follows:
• Generates debug event and Halt no later than the instruction following the next
Context Synchronization operation (CSO) excluding ISB instruction.
Unlinked Context matching and Address
mismatch breakpoints taken to Abort mode
The processor implements the following option:
• A Prefetch Abort debug exception is generated. Because the breakpoint is
configured to generate a breakpoint at PL1, the instruction at the Prefetch Abort
vector generates a Vector catch debug event.
Note
The debug event is subject to the same CONSTRAINED UNPREDICTABLE behavior,
therefore the Breakpoint debug event is repeatedly generated an UNKNOWN number of
times.
Vector catch on Data or Prefetch abort, and
taken to Abort mode
The processor implements the following option:
• A Prefetch Abort debug exception is generated. If Vector catch is enabled on the
Prefetch Abort vector, this generates a Vector catch debug event.
Note
The debug event is subject to the same CONSTRAINED UNPREDICTABLE behavior,
therefore the Breakpoint debug event is repeatedly generated an UNKNOWN number of
times.
H > N or H = 0 at Non-secure EL1 and EL0,
including value read from PMCR_EL0.N
The processor implements:
• A simple implementation where all of HPMN[4:0] are implemented, and In Non-
secure EL1 and EL0:
— If H > N then M = N.
— If H = 0 then M = 0.
H > N or H = 0: value read back in
MDCR_EL2.HPMN
The processor implements:
• A simple implementation where all of HPMN[4:0] are implemented and for reads
of MDCR_EL2.HPMN, return H.
P ≥ M and P ≠ 31: reads and writes of PM
XEVTYPER_EL0 and PMXEVCNTR_EL0
The processor implements:
• A simple implementation where all of SEL[4:0] are implemented, and if P ≥ M
and P ≠ 31 then the register is RES0.
P ≥ M and P ≠ 31: value read in
PMSELR_EL0.SEL
The processor implements:
• A simple implementation where all of SEL[4:0] are implemented, and if P ≥ M
and P ≠ 31 then the register is RES0.
B AArch32 UNPREDICTABLE Behaviors
B.4 Armv8 Debug UNPREDICTABLE behaviors
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English