Table C-4 Issue 0100-00
Change Location Affects
First release for r1p0 Revision history table
B2.83 Main ID Register, EL1 on page B2-510 and B1.96 Main ID Register
on page B1-313
B3.3 CPU Interface Identification Register on page B3-562.
B3.8 VM CPU Interface Identification Register on page B3-567.
C9.8 ROM Table Peripheral Identification Register 2 on page C9-680.
C10.14 Performance Monitors Peripheral Identification Register 2 on page C10-722.
C11.68 ETM Peripheral Identification Register 2 on page C11-816.
C12.8 CTI Peripheral Identification Register 2 on page C12-835.
MIDR and VPIDR reset values in B1.2 c0 registers on page B1-152 and
B1.20 AArch32 Identification registers on page B1-176.
MIDR_EL1 and VPIDR_EL2 reset values in B2.2 AArch64 Identification registers
on page B2-363.
GICV_IIDR reset value in B3.6 Virtual CPU interface register summary
on page B3-565.
GICC_IIDR reset value in B3.1 CPU interface register summary on page B3-560.
r1p0
Updated company name from
Arm to Arm
Entire manual All
versions
Updated all sections affected by
the addition of a new
asymmetric floating-point/
NEON feature
• A1.3 Implementation options on page A1-32
• A2.1 Components on page A2-40
• A.2 Processor configuration signals on page Appx-A-849
• A.7 Power management signals on page Appx-A-856
r1p0
Updated all sections affected by
the additional of the
CP15SDISABLE2 signal
• A2.3 About system control on page A2-46
• B1.47 Domain Access Control Register on page B1-221
• B1.95 Memory Attribute Indirection Registers 0 and 1 on page B1-310
• B1.98 Non-Secure Access Control Register on page B1-317
• B1.99 Normal Memory Remap Register on page B1-319
• B1.101 Primary Region Remap Register on page B1-322
• B1.105 System Control Register on page B1-331
• B1.106 Secure Debug Control Register on page B1-335
• B1.107 Secure Debug Enable Register on page B1-337
• B1.110 Translation Table Base Control Register on page B1-341
• B1.116 Translation Table Base Register 1 on page B1-350
• B1.119 Vector Base Address Register on page B1-354
• B2.79 Memory Attribute Indirection Register, EL3 on page B2-499
• B2.87 Reset Management Register, EL3 on page B2-519
r1p0
Fixed incorrect MRC/MCR
encodings
C10.2 Performance Monitors Control Register on page C10-692 All
versions
Clarified the L2 cache behavior
when disabled
A5.4 Disabling a cache on page A5-81 All
versions
Added warm reset information A3.3 Resets on page A3-52 All
versions
C Revisions
C.1 Revisions
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
Appx-C-894
Non-Confidential
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