EasyManuals Logo

ARM Cortex-A35 User Manual

Default Icon
894 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #893 background imageLoading...
Page #893 background image
Table C-2 Issue 0001-00 (continued)
Change Location Affects
Several reset values updated in
summary tables.
B1.12 c9 registers on page B1-167.
B1.26 AArch32 Performance monitor registers on page B1-183.
B2.10 AArch64 Performance monitor registers on page B2-373.
All versions
PMU events added to PMU events
table.
C2.3 Performance monitoring events on page C2-588. All versions
DTAH [24] bit updated.
B2.36 CPU Auxiliary Control Register, EL1 on page B2-412. All versions
ROM table for v7 added.
C9.4 ROM entry registers on page C9-673. All versions
Table C-3 Issue 0002-00
Change Location Affects
First release for r0p2. B2.83 Main ID Register, EL1 on page B2-510.
B3.3 CPU Interface Identification Register on page B3-562.
B3.8 VM CPU Interface Identification Register on page B3-567.
C8.10 External Debug Peripheral Identification Register 1 on page C8-659.
C9.8 ROM Table Peripheral Identification Register 2 on page C9-680.
C10.14 Performance Monitors Peripheral Identification Register 2 on page C10-722.
C11.13 Trace ID Register on page C11-750.
C11.68 ETM Peripheral Identification Register 2 on page C11-816.
C12.8 CTI Peripheral Identification Register 2 on page C12-835.
r0p2
Bits [9:0] updated in CPTR_EL3
and HCPTR.
B2.33 Architectural Feature Trap Register, EL3 on page B2-406.
B1.60 Hyp Architectural Feature Trap Register on page B1-237
All versions
References to internal memory-
mapped removed.
B1.96 Main ID Register on page B1-313.
B1.97 Multiprocessor Affinity Register on page B1-315.
B2.84 Multiprocessor Affinity Register, EL1 on page B2-512.
C7.1 AArch64 debug register summary on page C7-634.
C8.1 Memory-mapped debug register summary on page C8-644.
C10.1 AArch32 PMU register summary on page C10-690.
C10.9 Memory-mapped PMU register summary on page C10-714.
C12.1 Cross trigger register summary on page C12-826.
All versions
nSEI, nREI, and nVSEI clarified
in GIC signals table.
A.5 GIC signals on page Appx-A-852. All versions
C Revisions
C.1 Revisions
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
Appx-C-893
Non-Confidential

Table of Contents

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the ARM Cortex-A35 and is the answer not in the manual?

ARM Cortex-A35 Specifications

General IconGeneral
BrandARM
ModelCortex-A35
CategoryComputer Hardware
LanguageEnglish

Related product manuals