Table C8-1 Memory-mapped debug register summary (continued)
Offset Name Type Width Description
0x40C
- - - Reserved
0x410
DBGBVR1_EL1[31:0] RW 64 Debug Breakpoint Value Register 1
0x414
DBGBVR1_EL1[63:32]
0x418
DBGBCR1_EL1 RW 32 C7.2 Debug Breakpoint Control Registers, EL1 on page C7-636
0x41C
- - - Reserved
0x420
DBGBVR2_EL1[31:0] RW 64 Debug Breakpoint Value Register 2
0x424
DBGBVR2_EL1[63:32]
0x428
DBGBCR2_EL1 RW 32 C7.2 Debug Breakpoint Control Registers, EL1 on page C7-636
0x42C
- - - Reserved
0x430
DBGBVR3_EL1[31:0] RW 64 Debug Breakpoint Value Register 3
0x434
DBGBVR3_EL1[63:32]
0x438
DBGBCR3_EL1 RW 32 C7.2 Debug Breakpoint Control Registers, EL1 on page C7-636
0x43C
- - - Reserved
0x440
DBGBVR4_EL1[31:0] RW 64 Debug Breakpoint Value Register 4
0x444
DBGBVR4_EL1[63:32]
0x448
DBGBCR4_EL1 RW 32 C7.2 Debug Breakpoint Control Registers, EL1 on page C7-636
0x44C
- - - Reserved
0x450
DBGBVR5_EL1[31:0] RW 64 Debug Breakpoint Value Register 5
0x454
DBGBVR5_EL1[63:32]
0x458
DBGBCR5_EL1 RW 32 C7.2 Debug Breakpoint Control Registers, EL1 on page C7-636
0x45C-0x7FC
- - - Reserved
0x800
DBGWVR0_EL1[31:0] RW 64 Debug Watchpoint Value Register 0
0x804
DBGWVR0_EL1[63:32]
0x808
DBGWCR0_EL1 RW 32 C7.3 Debug Watchpoint Control Registers, EL1 on page C7-639
0x80C
- - - Reserved
0x810
DBGWVR1_EL1[31:0] RW 64 Debug Watchpoint Value Register 1
0x814
DBGWVR1_EL1[63:32]
0x818
DBGWCR1_EL1 RW 32 C7.3 Debug Watchpoint Control Registers, EL1 on page C7-639
0x81C
- - - Reserved
0x820
DBGWVR2_EL1[31:0] RW 64 Debug Watchpoint Value Register 2
0x824
DBGWVR2_EL1[63:32]
0x828
DBGWCR2_EL1 RW 32 C7.3 Debug Watchpoint Control Registers, EL1 on page C7-639
0x82C
- - - Reserved
0x830
DBGWVR3_EL1[31:0] RW 64 Debug Watchpoint Value Register 0,
0x834
DBGWVR3_EL1[63:32]
C8 Memory-mapped debug registers
C8.1 Memory-mapped debug register summary
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C8-645
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