ARM Cortex-A35 User Manual

Table B-1 Armv8 Debug UNPREDICTABLE behaviors (continued)
Scenario Behavior
Accessing reserved debug registers
The processor deviates from Preferred behavior because the hardware cost to decode
some of these addresses in debug power domain is significantly high:
Actual behavior:
1. For reserved debug and Performance Monitors registers the response is
CONSTRAINED UNPREDICTABLE Error or RES0, when any of the following
error instead of preferred RES0 for reserved debug registers
0x000-0xCFC and reserved PMU registers 0x000-0xF00:
Off
Core power domain is either completely off, or in a low-power
state where the Core power domain registers cannot be
accessed.
DLK
DoubleLockStatus() is TRUE, OS double-lock is locked,
that is, EDPRSR.DLK is 1.
OSLK
OSLSR_EL1.OSLK is1, OS lock is locked.
2. In addition, for reserved debug registers in the address ranges 0x400 to
0x4FC and 0x800 to 0x8FC, the response is CONSTRAINED
UNPREDICTABLE Error or RES0 when the conditions in 1 do not apply and:
EDAD
AllowExternalDebugAccess() is FALSE, external debug
access is disabled.
3. For reserved Performance Monitor registers in the address ranges 0x000
to 0x0FC and 0x400 to 0x47C, the response is CONSTRAINED
UNPREDICTABLE Error, or RES0 when the conditions in 1 and 2 do not
apply, and the following errors instead of preferred res0 for the these
registers:
EPMAD
AllowExternalPMUAccess() is FALSE (external
Performance Monitors access is disabled).
Clearing the clear-after-read EDPRSR bits
when Core power domain is on, and
DoubleLockStatus() is TRUE
The processor behaves as indicated in the sole Preference:
• Bits are not cleared to zero.
B AArch32 UNPREDICTABLE Behaviors
B.4 Armv8 Debug UNPREDICTABLE behaviors
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English