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ABB AC500 PLC - Page 398

ABB AC500 PLC
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Terminal Signal Description
12 I3- Negative pole of input signal 3
13 --- Reserved
14 --- Reserved
15 --- Reserved
16 --- Reserved
17 --- Reserved
18 SG Signal ground
19 L+ Process voltage L+ (24 VDC)
20 M Process voltage M (0 VDC)
The internal power supply voltage for the module's circuitry is carried out via the I/O bus (pro-
vided by a bus module or a CPU). Thus, the current consumption from 24 VDC power supply at
the terminals L+/UP and M/ZP of the CPU/bus module increases by 10 mA per AI561.
The external power supply connection is carried out via the L+ (+24 VDC) and the M (0 VDC)
terminals. The M terminal is electrically interconnected to the M/ZP terminal of the CPU/bus
module.
NOTICE!
Risk of imprecise and faulty measurements!
Analog signals may be distorted seriously by external electromagnetic influ-
ences.
Use shielded wires when wiring analog signal sources. The cable shield must
be grounded at both ends of the cable. Provide a potential equalisation of a low
resistance to avoid high potential differences between different parts of the
plant.
NOTICE!
Risk of damaging the PLC modules!
The PLC modules must not be removed while the plant is connected to a power
supply.
Make sure that all voltage sources (supply and process voltage) are switched
off before you
connect or disconnect any signal or terminal block
remove or replace a module.
NOTICE!
Risk of damaging the PLC modules!
Overvoltages and short circuits might damage the PLC modules.
Make sure that all voltage sources (supply and process voltage) are
switched off before you begin with operations at the system.
Never connect any voltages or signals to reserved terminals (marked with
---). Reserved terminals may carry internal voltages.
The module provides several diagnosis functions
Ä
Chapter 1.5.2.1.1.6 “Diagnosis”
on page 401.
The following figure is an example of the internal construction of the analog input AI0. The
analog inputs AI1...AI3 are designed in the same way.
Device Specifications
I/O Modules > Analog I/O Modules
2019/04/173ADR010121, 13, en_US398

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