NXP Semiconductors MPC5566 - Pad Configuration Register 70 (SIU_PCR70)

System Integration Unit (SIU)
MPC5566 Microcontroller Reference Manual, Rev. 2
6-42 Freescale Semiconductor
Refer to Table 6-19 for bit field definitions. Table 6-43 lists the PA fields for TS_GPIO[69].
6.3.1.43 Pad Configuration Register 70 (SIU_PCR70)
The SIU_PCR70 register controls the function, direction, and electrical attributes of the TA_GPIO[70].
Figure 6-44. TA_GPIO[70] Pad Configuration Register (SIU_PCR70)
Refer to Table 6-19 for bit field definitions. Table 6-46 lists the PA fields for TA_GPIO[70].
6.3.1.44 Pad Configuration Register 71 (SIU_PCR71)
The SIU_PCR71 register controls the function, direction, and electrical attributes of TEA_GPIO[71].
Table 6-43. PCR69 PA Field Definition
PA Field Pin Function
0b0 GPIO[69]
0b1 TS
Address: Base + 0x00CC Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0
PA OBE
1
1
When configured as TA, the OBE bit has no effect. When configured as GPDO, set the OBE bit to 1.
IBE
2
2
When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register.
Clear the IBE bit to 0 to reduce power consumption. When configured as GPDI, set the IBE bit to 1.
DSC ODE
3
3
When configured as TA and external master operation is enabled, clear the ODE bit to 0.
HYS
4
4
When EBI is enabled, clear the HYS bit to 0.
0 0
WPE
5
5
Refer to the EBI section for weak pullup settings when configured as TA.
WPS
5
W
RESET: 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1
Table 6-44. PCR70 PA Field Definition
PA Field Pin Function
0b0 GPIO[70]
0b1 TA