Deserial Serial Peripheral Interface (DSPI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 20-67
in the DSPI return the correct values when read, but writing to them has no affect. Writing to the
DSPIx_TCR during module disable mode does not have an effect. Interrupt and DMA request signals
cannot be cleared while in the module disable mode.
20.4.10.2 Slave Interface Signal Gating
The DSPI module enable signal is used to gate slave interface signals such as address, byte enable,
read/write and data. This prevents toggling slave interface signals from consuming power unless the DSPI
is accessed.
20.5 Initialization and Application Information
20.5.1 How to Change Queues
DSPI queues are not part of the DSPI module, but the DSPI includes features in support of queue
management. Queues are primarily supported in SPI configuration. This section presents an example of
how to change queues for the DSPI.
1. Set the EOQ bit in the command word to indicate the last entry in the queue for the DSPI after the
last command word from a queue is executed.
2. Sample the command word that has the EOQ bit set at the end of the transfer. Set the EOQ flag
(EOQF) in the DSPIx_SR is set.
If EOQF flag is set to 1, the serial interface is disabled, preventing data transmission and reception.
The DSPI is put into the STOPPED state and the TXRXS bit is negated to indicate the STOPPED
state. The eDMA continues to fill the TX FIFO until one of the following conditions occur:
— TX FIFO is full
— Modified DMA descriptor that adds queues to the TX and RX channels is received (step 5).
3. Disable the DSPI DMA transfers by clearing the DMA channel enable bit for the DMA channel
assigned to the TX FIFO and RX FIFO. This is done in the eDMA controller.
4. Ensure all received data in the RX FIFO was transferred to the memory receive queue using one
of the following methods:
— Read RXCNT in DSPIx_SR
— Check RFDF in the DSPIx_SR after each read operation of the DSPIx_POPR.
5. Modify the DMA descriptor for the TX and RX channels for additional queues.
6. Flush the TX FIFO and RX FIFO by writing a 1 to the CLR_TXF and the CLR_RXF bits
respectively in the DSPIx_MCR register.
7. Clear the transfer count using one of the following methods:
— Set the CTCNT bit in the command word of the first entry in the new queue
— Write directly to SPI_TCNT field in DSPIx_TCR
8. Enable the DMA channel by setting the DMA enable request bit for the DMA channel assigned to
the DSPI TX and RX FIFOs.
9. Enable serial transmission and serial reception of data by clearing the EOQF bit.
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