NXP Semiconductors MPC5566 - Pad Configuration Register 299 (SIU_PCR299)

System Integration Unit (SIU)
MPC5566 Microcontroller Reference Manual, Rev. 2
6-106 Freescale Semiconductor
Refer to Table 6-19 for bit field definitions. Table 6-145 lists the PA fields for CAL_TS.
6.3.1.158 Pad Configuration Register 299 (SIU_PCR299)
The SIU_PCR299 register controls the function, direction, and electrical attributes of
CAL_CS[1]_CAL_ADDR[9].
Figure 6-158. CAL_CS[1]_CAL_ADDR[9] Pad Configuration Registers (SIU_PCR299)
Refer to Table 6-19 for bit field definitions. Table 6-146 lists the PA fields for
CAL_CS[1]_CAL_ADDR[9].
6.3.1.159 GPIO Pin Data Output Registers 0–213 (SIU_GPDOn)
The 8-bit SIU_GPDOn registers defined in Figure 6-159 each specify the output data for the function
assigned to the GPIO[n] pin. The n notation in the 214 SIU_GPDOn register names relate to the [n] in
GPIO[n] signal name. For example, SIU_GPDO0 contains the PDO0 bit for CS
[0]_GPIO[0]; and
SIU_GPDO213 contains the PDO213 bit for WKPCFG_GPIO[213]. The address for a GPDO pin is the
GPIO number plus an offset of SIU_BASE + 0x0600.
Software writes to the SIU_GPDOn registers to drive data out on the external pin. Each register drives one
external pin, which allows independent control of the pin. Writes to the SIU_GPDOn registers have no
effect if an input function is assigned to the pin by the pad configuration register.
If the direction of a GPIO signal changes from input to output, the SIU_GPDOn register value is
automatically driven out to the external pin without a software update.
Table 6-145. PCR298 PA Field Definition
PA Field Pin Function
0b0 Invalid value
0b1 CAL_TS
Address: Base + 0x0296 Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0
PA
0 0
DSC
0 0 0 0 0 0
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 6-146. PCR299 PA Field Definitions
PA Field Pin Function
0b00 Invalid value
0b01 CAL_CS
[1]
0b10 CAL_ADDR[9]
0b11 CAL_CS
[1]