NXP Semiconductors MPC5566 - External Interrupt Status Register (SIU_EISR)

System Integration Unit (SIU)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 6-15
The following table describes the fields in the system reset control register:
6.3.1.4 External Interrupt Status Register (SIU_EISR)
The external interrupt status register is used to record edge-triggered events on the IRQ[0]–IRQ[15] inputs
to the SIU. When an edge-detect enable bit is set in the SIU_IREER or SIU_IFEER registers for an IRQ
and an IRQ edge-event occurs and is detected, the IRQ flag bit is set in the SIU_EISR. The IRQ flag bits
are cleared by writing a 1 to the bit. A write of 0 has no effect.
The IRQ flag bit is set regardless of the state of the DMA or interrupt request enable bit in SIU_DIRER.
The IRQ flag bit remains set until cleared by software or through the servicing of a DMA or interrupt
request.
Table 6-10. SIU_SRCR Field Descriptions
Field Description
0
SSR
Software system reset.
The software system reset is processed as a synchronous reset. Except for a software external reset, the bit
automatically clears if any other reset source asserts.
0 No software system reset.
1 Generate an software internal system reset.
1
SER
Software external reset. Used to generate a software external reset. Writing a 1 to this bit asserts RSTOUT
for 2400
clocks, and the internal reset is not asserted. The bit automatically clears when the software external reset completes
or any other reset source is asserted. After a software external reset has been initiated, RSTOUT negates if this bit
is cleared before the 2400 clock period expires.
0 Do not generate a software external reset.
1 Generate a software external reset.
Note: If the FMPLL is configured for dual controller mode, a write of 1 to the SER bit asserts RSTOUT
for 16000
clocks. Refer to Section 4.2.2, “Reset Output (RSTOUT).”
2–15 Reserved
16
CRE
Checkstop reset enable. Write a 1 to this bit to enable the checkstop reset request input is asserted. The checkstop
reset request input is a synchronous internal reset source. The CRE bit defaults to checkstop reset enabled at POR.
If this bit is cleared, it remains cleared until the next POR.
0 No reset occurs when the checkstop reset input to the reset controller is asserted.
1 A reset occurs when the checkstop reset input to the reset controller is asserted.
17–31 Reserved