NXP Semiconductors MPC5566 - Features

Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5566 Microcontroller Reference Manual, Rev. 2
19-4 Freescale Semiconductor
For users familiar with the QADC, the eQADC system upgrades the functionality provided by that
module. Refer to Section 19.5.7, “eQADC versus QADC,” for a comparison between the eQADC and
QADC.
19.1.3 Features
The eQADC includes these distinctive features:
• Two independent on-chip RSD cyclic ADCs
— 12 bit AD resolution.
— Targets up to 10 bit accuracy at 400 kilosamples per second (ADC_CLK = 6 MHz) and eight
bit accuracy at 800 kilosamples per second (ADC_CLK = 12 MHz) for differential
conversions.
— Differential conversions (range -2.5 V to +2.5 V).
— Single-ended signal range from 0–5 V.
— Sample times of two (default), 8, 64, or 128 ADC clock cycles.
— Sample time stamp information when requested.
— Parallel interface to eQADC CFIFOs and RFIFOs.
— Supports right-justified unsigned and signed formats for conversion results.
• Optional automatic application of ADC calibration constants: provision of reference voltages
(25% V
REF
1
and 75% V
REF
) for ADC calibration purposes
• 40 input channels available to the two on-chip ADCs
• Four pairs of differential analog input channels
• Full duplex synchronous serial interface to an external device
— A free-running clock is provided for use by the external device
— Supports a 26-bit message length
— Transmits a null message when there are no triggered CFIFOs with commands bound for
external command buffers, or when there are triggered CFIFOs with commands bound for
external command buffers but the external command buffers are full
• Priority-based CFIFOs
— Supports six CFIFOs with fixed priority. The lower the CFIFO number, the higher its priority.
Supports software and several hardware trigger modes to arm a particular CFIFO.
— Generates interrupt when command coherency is not achieved.
• External hardware triggers
— Supports rising edge, falling edge, high level and low level triggers
— Supports configurable digital filter
• Upgrades the functionality of the QADC
1. V
REF
= V
RH
- V
RL
.