External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 12-13
NOTE
The open drain mode of the pads configuration module is not used for any
EBI signals. For a description of how signals are driven by multiple devices
in external master mode, see Section 12.4.2.10, “Bus Operation in External
Master Mode.”
12.3 Memory Map and Register Definition
Table 12-6 is a memory map of the EBI registers.
1
These signals are muxed with the chip select (CS) signals on this device. Use the pad configuration registers (PCR) in
the system integration module (SIU) to configure the balls to use the address signals or chip select signals–not both.
2
All I/O signals are three-stated by the EBI when not actively involved in a transfer.
3
Although external master accesses can drive these pins, the EBI three-states the pins and does not sample them for
input.
4
This device is designed to support a 32-bit EBI data bus (DATA[0:31]) and four write/byte enable signals (WE/BE[0:3])
using the VertiCal assembly.
5
The calibration signals for this device are available on the VertiCal assembly only.
Table 12-6. EBI Memory Map
Address Register Name Register Description Bits
Base (0xC3F8_4000) EBI_MCR EBI module configuration register 32
Base + 0x0004 — Reserved —
Base + 0x0008 EBI_TESR EBI transfer error status register 32
Base + 0x000C EBI_BMCR EBI bus monitor control register 32
Base + 0x0010 EBI_BR0 EBI base register bank 0 32
Base + 0x0014 EBI_OR0 EBI option register bank 0 32
Base + 0x0018 EBI_BR1 EBI base register bank 1 32
Base + 0x001C EBI_OR1 EBI option register bank 1 32
Base + 0x0020 EBI_BR2 EBI base register bank 2 32
Base + 0x0024 EBI_OR2 EBI option register bank 2 32
Base + 0x0028 EBI_BR3 EBI base register bank 3 32
Base + 0x002C EBI_OR3 EBI option register bank 3 32
Base + 0x0058 EBI_CAL_BR3 EBI calibration base register bank 3 32
Base + 0x005C EBI_CAL_OR3 EBI calibration option register bank 3 32
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