MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 8-1
Chapter 8  
Error Correction Status Module (ECSM)
8.1 Introduction
The device includes error-correcting code (ECC) implementations to improve the quality and reliability of 
internal SRAM and internal flash memories. The error correction status module (ECSM) allows the 
application to collect information on memory errors reported by ECC and/or generic access error 
information.
8.1.1 Overview
The ECSM provides a set of registers that configure and report ECC errors for the device including 
accesses to SRAM and flash memory. The application can configure the device for the types of memory 
errors to report, and then query a set of read-only status and information registers to identify any errors 
that have occurred. 
There are two types of ECC errors: correctable and non-correctable. A correctable ECC error is generated 
when only one bit is incorrect in a 64-bit doubleword. In this case, it is corrected automatically by 
hardware, and no flags or other indicators are set by the error that occurred. A non-correctable ECC error 
is generated when two bits in a 64-bit doubleword are incorrect. Non-correctable ECC errors cause an 
interrupt, and if enabled, additional error details are available in the ECSM.
Error correction is implemented on 64 data bits at a time, using eight ECC bits for every 64-bit doubleword 
of data. The ECC is checked on read accesses, and calculated on write accesses using the following 
sequence:
1. Read the 64 bits that contain the desired byte / halfword / word or doubleword in memory, and 
check the ECC.
2. If the access is a write, then:
a) Merge the new byte / halfword / word into the 64 data bits and calculate a new ECC value.
b) Write the 64 bits and the new ECC to SRAM.
To use the ECC for SRAM, write to SRAM memory before you enable the ECC. Refer to Section 8.3, 
“Initialization and Application Information.”
8.1.2 Features
The ECSM includes these features:
• Configurable for reporting non-correctable errors
• Registers for capturing ECC information for RAM and flash access errors