Interrupt Controller (INTC)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 10-31
10.4.3 Details on Handshaking with Processor
10.4.3.1 Software Vector Mode Handshaking
10.4.3.1.1 Acknowledging Interrupt Request to Processor
A timing diagram of the interrupt request and acknowledge handshaking in software vector mode, along
with the handshaking near the end of the interrupt exception handler, is shown in Figure 10-14. The INTC
examines the peripheral and software settable interrupt requests. When it finds an asserted peripheral or
software settable interrupt request with a higher priority than PRI in INTC current priority register
(INTC_CPR), it asserts the interrupt request to the processor. The INTVEC field in INTC interrupt
acknowledge register (INTC_IACKR) is updated with the preempting interrupt request’s vector when the
interrupt request to the processor is asserted. The INTVEC field retains that value until the next time the
interrupt request to the processor is asserted. The rest of the handshaking is described in Section 10.1.4.1,
“Software Vector Mode.”
10.4.3.1.2 End-of-Interrupt Exception Handler
Before the interrupt exception handling completes, INTC end-of-interrupt register (INTC_EOIR) must be
written. When it is written, the LIFO is popped so that the preempted priority is restored into PRI of the
INTC_CPR. Before it is written, the peripheral or software settable flag bit must be cleared so that the
peripheral or software settable interrupt request is negated.
NOTE
To ensure proper operation across all Power Architecture MCUs, execute an
MBAR or MSYNC instruction between the access to clear the flag bit and the
write to the INTC_EOIR.
When returning from the preemption, the INTC does not search for the peripheral or software settable
interrupt request whose ISR was preempted. Depending on how much the ISR progressed, that interrupt
request can no longer be asserted. When PRI in INTC_CPR is lowered to the priority of the preempted
ISR, the interrupt request for the preempted ISR or any other asserted peripheral or software settable
interrupt request at or below that priority does not cause a preemption. Instead, after the restoration of the
preempted context, the processor returns to the instruction address that it was to next execute before it was
preempted. This next instruction is part of the preempted ISR or the interrupt exception handler’s prolog
or epilog.
To Next Page
Loading...
