NXP Semiconductors MPC5566 - FIFO Transmit FIFO Watermark Register (TFWR)

Fast Ethernet Controller (FEC)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 15-27
15.3.4.2.18 FIFO Transmit FIFO Watermark Register (TFWR)
The TFWR is a 32-bit read/write register with one 2-bit field programmed by the application to control the
amount of data required in the transmit FIFO before transmission of a frame can begin. This allows the
application to minimize transmit latency (TFWR = 0x) or allow for larger bus access latency (TFWR = 11)
due to contention for the system bus. Setting the watermark to a high value minimizes the risk of a transmit
FIFO underrun due to contention for the system bus. The byte counts of the TFWR field can require
modification to match a given system requirement.
Address: Base + 0x0124 Access: User R/W
0 123456789101112131415
R
GADDR2
W
Reset U
1
UU U U U U U U U U UUU U U
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
GADDR2
W
Reset U U U U U U U U U U U U U U U U
1
“U” signifies a bit that is uninitialized. See the Preface of the book.
Figure 15-21. Descriptor Group Lower Address Register (GALR)
Table 15-21. GALR Field Descriptions
Field Description
0–31
GADDR2
The GADDR2 register contains the lower 32 bits of the 64-bit hash table used in the address recognition
process for receive frames with a multicast address. Bit 31 of GADDR2 contains hash index bit 31. Bit 0
of GADDR2 contains hash index bit 0.
Address: Base + 0x0144 Access: User R/W
0 1 2 3 4 5 6 7 8 9 1011121314 15
R000000000000000 0
W
Reset000000000000000 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R00000000000000X_WMRK
W
Reset000000000000000 0
Figure 15-22. FIFO Transmit FIFO Watermark Register (TFWR)