NXP Semiconductors MPC5566 - Emios Output Update Disable Register (EMIOS_OUDR)

Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5566 Microcontroller Reference Manual, Rev. 2
17-10 Freescale Semiconductor
17.3.1.3 eMIOS Output Update Disable Register (EMIOS_OUDR)
The EMIOS_OUDR serves to disable transfers from the A2 to the A1 channel registers and from the B2
to the B1 channel registers when values are written to these registers, and the channel is running in
modulus counter (MC) mode or an output mode.
The following table describes the fields in the eMIOS output update disable register:
Address: Base + 0x0004 Access: R/O
0123456789101112131415
R00000000F23F22F21F20F19F18F17F16
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RF15F14F13F12F11F10F9F8F7F6F5F4F3F2F1F0
W
Reset0000000000000000
Figure 17-3. eMIOS Global Flag Register (EMIOS_GFR)
Address: Base + 0x0008 Access: R/W
0123456789101112131415
R00000000
OU23 OU22 OU21 OU20 OU19 OU18 OU17 OU16
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
OU15 OU14 OU13 OU12 OU11 OU10 OU9 OU8 OU7 OU6 OU5 OU4 OU3 OU2 OU1 OU0
W
Reset0000000000000000
Figure 17-4. eMIOS Output Update Disable Register (EMIOS_OUDR)
Table 17-7. EMIOS_OUDR Field Descriptions
Field Description
0–7 Reserved.
8–31
OUn
Channel n output update disable. When running in MC mode or an output mode, values are written to registers A2
and B2. OUn bits are used to disable transfers from registers A2 to A1 and B2 to B1. Each bit controls one channel.
0 Transfer enabled. Depending on the operating mode, transfer occurs immediately or in the next period. Unless
stated otherwise, transfer occurs immediately.
1 Transfers disabled