NXP Semiconductors MPC5566 - Receive Descriptor Active Register (RDAR)

Fast Ethernet Controller (FEC)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 15-13
Table 15-5 describes the fields and functions of the Ethernet interrupt event register:
15.3.4.2.3 Receive Descriptor Active Register (RDAR)
RDAR is a command register, written by the application, that indicates that the receive descriptor ring has
been updated (empty receive buffers were produced by the driver with the empty bit set).
Whenever the register is written, the R_DES_ACTIVE bit is set. This is independent of the data actually
written by the application. When set, the FEC polls the receive descriptor ring and process receive frames
(provided ECR[ETHER_EN] is also set). Once the FEC polls a receive descriptor with an empty bit that
is cleared to 0, the FEC clears R_DES_ACTIVE and stops receive descriptor ring polling until the bit is
set again, signifying that additional descriptors were placed into the receive descriptor ring.
The RDAR register is cleared at reset and when ECR[ETHER_EN] is cleared.
Address: Base + 0x0008 Access: User R/W
0 123456789101112131415
RHB
ERR
BABR BABT GRA TXF TXB RXF RXB MII
EB
ERR
LC RL UN
000
W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0000000000 000000
W
Reset0000000000000000
Figure 15-4. Interrupt Mask Register (EIMR)
Table 15-5. EIMR Field Descriptions
Field Description
0–12
See Figure 15-4
and Table 15-4.
Interrupt mask. Each bit corresponds to an interrupt source defined by the EIR register. The
corresponding EIMR bit determines whether an interrupt condition can generate an interrupt.
0 The corresponding interrupt source is masked.
1 The corresponding interrupt source is not masked.
Write 1 to clear.
13–31 Reserved, must be cleared.