NXP Semiconductors MPC5566 - Pad Configuration Registers 211-212 (SIU_PCR211-SIU_PCR212)

System Integration Unit (SIU)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 6-91
6.3.1.119 Pad Configuration Registers 211–212 (SIU_PCR211–SIU_PCR212)
The SIU_PCR211–SIU_PCR212 registers control the function, direction, and electrical attributes of
BOOTCFG[0:1]_IRQ[2:3]_GPIO[211:212].
Figure 6-120. BOOTCFG[0:1]_IRQ[2:3]_GPIO[211:212]
Pad Configuration Register (SIU_PCR211–SIU_PCR212)
Refer to Table 6-19 for bit field definitions. Table 6-117 lists the PA fields for
BOOTCFG[0:1]_IRQ[2:3]_GPIO[211:212].
6.3.1.120 Pad Configuration Register 213 (SIU_PCR213)
The SIU_PCR213 register controls the function, direction, and electrical attributes of
WKPCFG_GPIO[213].
Figure 6-121. WKPCFG_GPIO[213] Pad Configuration Register (SIU_PCR213)
Address: Base + (0x01E6–0x01E8) Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0
PA
1
1
The BOOTCFG[0:1] function applies only during reset when the RSTCFG pin is asserted during reset. Set the PA field to 0b10
for IRQ
[2:3], or to 0b00 for GPIO[211:212].
OBE
2
2
When configured as IRQ[2:3], the OBE bit has no effect. When configured as GPDO, set the OBE bit to 1.
IBE
3
3
When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register. Clear the IBE bit to 0
to reduce power consumption. When configured as GPDI, set the IBE bit to 1.
0 0
ODE HYS
4
4
When configured as IRQ[2:3], set the HYS bit to 1.
SRC WPE WPS
W
RESET: 0 0 0 0 1 1 0 0 0 0 0 1 0 0 1 0
Table 6-117. PCR211–PCR212 PA Field Definitions
PA Field Pin Function
0b00 GPIO[211:212]
0b01 BOOTCFG[0:1]
0b10 IRQ[2:3]
0b11 BOOTCFG[0:1]
Address: Base + 0x01EA Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0
PA
1
1
WKPCFG function is only applicable during reset. The PA bit must be cleared to 0 for GPIO operation.
OBE
2
2
When configured as GPDO, set the OBE bit to 1.
IBE
3
3
When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the corresponding GPDI register. When
configured as GPDI, set the IBE bit to 1.
0 0
ODE HYS SRC WPE WPS
W
RESET: 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 1