Fast Ethernet Controller (FEC)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 15-11
15.3.4.2 FEC Registers
The following sections describe each FEC register in detail. The base address of these registers is
0xFFF4_C000.
15.3.4.2.1 Ethernet Interrupt Event Register (EIR)
When an event occurs that sets a bit in the Ethernet Interrupt Event register (EIR), an interrupt is generated
if the corresponding bit in the interrupt mask register (EIMR) is also set. The bit in the EIR is cleared if a
one is written to that bit position; writing zero has no effect. This register is cleared upon hardware reset.
These interrupts can be divided into operational interrupts, transceiver or network error interrupts, and
internal error interrupts. Interrupts which can occur in normal operation are GRA, TXF, TXB, RXF, RXB,
and MII. Interrupts resulting from errors/problems detected in the network or transceiver are HBERR,
BABR, BABT, LC, and RL. Interrupts resulting from internal errors are HBERR and UN.
Some of the error interrupts are independently counted in the MIB block counters. Software can mask the
following interrupts since the errors are visible to network management using the following MIB counters:
HBERR IEEE_T_SQE
BABR RMON_R_OVERSIZE (valid CRC), RMON_R_JAB (invalid CRC)
BABT RMON_T_OVERSIZE (valid CRC), RMON_T_JAB (invalid CRC)
LATE_COL IEEE_T_LCOL
COL_RETRY_LIM IEEE_T_EXCOL
XFIFO_UN IEEET_MACERR
Table 15-2 shows the Ethernet interrupt event register (EIR):
Table 15-4 describes the fields and functions of the Ethernet interrupt event register:
Address: Base + 0x0004 Access: User R/W
0 123456789101112131415
RHB
ERR
BABR BABT GRA TXF TXB RXF RXB MII
EB
ERR
LC RL UN
000
Ww1c
1
1
“w1c” signifies the bit is cleared by writing 1 to it.
w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0000000000 000000
W
Reset0000000000000000
Figure 15-3. Ethernet Interrupt Event Register (EIR)
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