NXP Semiconductors MPC5566 - Chapter 17 Emios Operating Modes

Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5566 Microcontroller Reference Manual, Rev. 2
17-4 Freescale Semiconductor
17.1.3 eMIOS Operating Modes
The eMIOS has the following operating modes:
17.1.3.1 Unified Channel Modes
The unified channels can be configured to operate in the following modes:
• General purpose input/output
• Single action input capture
• Single action output compare
• Input pulse-width measurement
• Input period measurement
• Double action output compare
• Pulse/edge accumulation
• Pulse/edge counting
• Quadrature decode
• Windowed programmable time accumulation
• Modulus counter, normal
• Modulus counter, buffered
• Output pulse-width and frequency modulation, normal
• Output pulse-width and frequency modulation, buffered
• Center-aligned output pulse-width modulation with dead time insertion, normal
• Center-aligned output pulse-width modulation with dead time insertion, buffered
• Output pulse-width modulation, normal
• Output pulse-width modulation, buffered
These modes are described in Section 17.4.4.4, “Unified Channel Operating Modes.”
Table 17-1. eMIOS Operating Modes
Mode Description
User
User mode is the normal operating mode. When EMIOS_MCR[FRZ] = 0, and EMIOS_CCR[FREN] = 0,
the eMIOS is in user mode.
Debug
Debug mode is individually programmed for each channel. When entering this mode, the UC registers’
contents are frozen, but remain available for read and write access through the slave interface. After
leaving debug mode, all counters that were frozen upon debug mode entry resume at the point where
they were frozen.
In debug mode, all clocks are running and all registers are accessible; thus, this mode is not intended for
power saving, but for use during software debugging.
Freeze
Freeze mode enables the eMIOS to freeze the registers of the unified channels when debug mode is
requested at the MCU level. While in freeze mode, the eMIOS continues to operate to allow the MCU
access to the unified channels’ registers. The unified channel remains frozen until the EMIOS_MCR[FRZ]
bit is cleared to zero, the MCU exits debug mode, or a unified channel’s EMIOS_CCR[FREN] bit is
cleared.