Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 17-9
17.3.1.2 eMIOS Global Flag Register (EMIOS_GFR)
The EMIOS_GFR is a read-only register that groups the FLAG bits from all channels. This organization
improves interrupt handling on simpler devices. These bits are mirrors of the FLAG bits of each channel
register (EMIOS_CSR) and flag bits in those channel registers cannot be cleared by accessing this ‘mirror’
register.
4
ETB
External time base. Selects the time base source that drives counter bus [A].
0 Unified channel 23 drives counter bus [A]
1 STAC drives counter bus [A]
Note: If ETB is set to select STAC as the counter bus[A] source, the GTBE must be set to enable the STAC to
counter bus[A]. See Section 17.4.2, “STAC Client Submodule” and the shared time and angle clock
(STAC) bus interface section and the STAC bus configuration register (ETPU_REDCR) section of the
eTPU chapter for more information about the STAC.
5
GPREN
Global prescaler enable. Enables the prescaler counter.
0 Prescaler disabled (no clock) and prescaler counter is cleared
1 Prescaler enabled
6–11 Reserved.
12–15
SRV[0:3]
Server time slot. Selects the address of a specific STAC server to which the STAC client submodule is
assigned (refer to Section 17.4.2, “STAC Client Submodule,” for details)
0000 eTPU engine A, TCR1
0001 eTPU engine B, TCR1
0010 eTPU engine A, TCR2
0011 eTPU engine B, TCR2
0100–1111 reserved
16–23
GPRE[0:7]
Global prescaler. Selects the clock divider value for the global prescaler, as shown here:
24–31 Reserved.
1
The GTBE signal is an inter-module signal, not an external pin on the device.
Table 17-6. EMIOS_MCR Field Descriptions (continued)
Field Description
GPRE[0:7] Divide Ratio
00000000 1
00000001 2
.
.
.
.
.
.
.
.
11111111 256
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