NXP Semiconductors MPC5566 - Peripheral Interrupt Requests

Interrupt Controller (INTC)
MPC5566 Microcontroller Reference Manual, Rev. 2
10-28 Freescale Semiconductor
NOTE
The peripheral or software settable interrupt request asserts when the PRIn
value in the interrupt priority select register (INTC_PSRn) is greater than
the PRIn value in interrupt current priority register (INTC_CPR).
If an asserted peripheral or software settable interrupt request negates before
the processor acknowledges its request, the interrupt request can reassert
and remain asserted. If this occurs, the processor uses the INTC_PSRn value
to locate the IRQ vector, and updates the PRIn value in the INTC_CPR with
the PRIn value in INTC_PSRn.
Clearing the peripheral interrupt request enable bit for the peripheral
initiating the request, or setting the IRQ mask bit has the same consequences
as clearing its flag bit. Setting its enable bit or clearing its mask bit while its
flag bit is asserted has the same effect on the INTC as an interrupt event
setting the flag bit.
10.4.1.1 Peripheral Interrupt Requests
An interrupt event in a peripheral’s hardware sets a flag bit which resides in that peripheral. The interrupt
request from the peripheral is driven by that flag bit.
The time from when the peripheral starts to drive its peripheral interrupt request to the INTC to the time
that the INTC starts to drive the interrupt request to the processor is three clocks.
10.4.1.2 Software Settable Interrupt Requests
The software set/clear interrupt registers (INTC_SSCIRx_x) support the setting or clearing of
software-settable interrupt requests. These registers contain eight independent sets of bits to set and clear
a corresponding flag bit by software. With the exception of being set by software, this flag bit behaves the
same as a flag bit set within a peripheral. This flag bit generates an interrupt request within the INTC just
like a peripheral interrupt request.
An interrupt request is triggered by software writing a 1 to the SETn bit in INTC software set/clear
interrupt registers (INTC_SSCIR0–INTC_SSCIR7). This write sets a CLRn flag bit that generates an
0x1480 328 CAND_IFRH[BUF63:BUF32] FlexCAN D buffers 63–32 interrupts
0x1490–0x14B0 329–331 Reserved
1
The vector number is used to identify the interrupt priority select register; it does not indicate the maximum number of usable
interrupt sources.
2
Interrupt requests from the same module location are ORed together.
Table 10-9. MPC5566 Interrupt Request Sources (continued)
Hardware
Vector Mode
Offset
Vector
Number
1
Source
2
Description