NXP Semiconductors MPC5566 - Pad Configuration Register 105 (SIU_PCR105)

System Integration Unit (SIU)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 6-59
Refer to Table 6-19 for bit field definitions. Table 6-44 lists the PA fields for
SOUTB_PCSC[5]_GPIO[104].
6.3.1.71 Pad Configuration Register 105 (SIU_PCR105)
The SIU_PCR105 register controls the function, direction, and electrical attributes of
PCSB[0]_PCSD[2]_GPIO[105].
Figure 6-72. PCSB[0]_PCSD[2]_GPIO[105] Pad Configuration Register (SIU_PCR105)
Refer to Table 6-19 for bit field definitions. Table 6-71 lists the PA fields for
PCSB[0]_PCSD[2]_GPIO[105].
Table 6-70. PCR104 PA Field Definitions
PA Field Pin Function
0b00 GPIO[104]
0b01 SOUTB
0b10 PCSC[5]
0b11 SOUTB
Address: Base + 0x0112 Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0
PA OBE
1
1
When configured as PCSB[0], set the OBE bit to 1 for master operation, or clear to 0 for slave operation. When configured as
PCSD[2], the OBE bit has no effect. When configured as GPDO, set the OBE bit to 1.
IBE
2
2
When configured as PCSB[0] in slave operation, set the IBE bit to 1. When the pad is configured as an output, set the IBE bit
to 1 to show the pin state in the GPDI register. Clear the IBE bit to 0 to reduce power consumption. When configured as GPDI,
set the IBE bit to 1.
0 0
ODE HYS SRC WPE WPS
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Table 6-71. PCR105 PA Field Definitions
PA Field Pin Function
0b00 GPIO[105]
0b01 PCSB[0]
0b10 PCSD[2]
0b11 PCSB[0]