Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 19-45
Figure 19-25. Result Flow During eQADC Operation
19.4.1.1 Assumptions/Requirements Regarding the External Device
The external device exchanges command and result data with the eQADC through the eQADC SSI
interface. This section explains the minimum requirements an external device has to meet to properly
interface with the eQADC. Some assumptions about the architecture of the external device are also
described.
19.4.1.1.1 eQADC SSI Protocol Support
The external device must fully support the eQADC SSI protocol as specified in Section 19.4.8, “eQADC
Synchronous Serial Interface (SSI) Submodule,” section of this document. Support for the abort feature is
optional. When aborts are not supported, all command messages bound for an external command buffer
must have the ABORT_ST bit negated - see Section , “ Command Message Format for External Device
Operation.”
19.4.1.1.2 Number of Command Buffers and Result Buffers
The external device should have a minimum of one and a maximum of two command buffers to store
command data sent from the eQADC. If more than two command buffers are implemented in the external
device, they are not recognized by the eQADC as valid destinations for commands. In this document, the
two valid external command buffers are referred to as command buffer 2 and command buffer 3 (the two
on-chip ADCs being command buffer 0 and 1). The external device decides to which external command
buffer a command should go by decoding the upper bit (BN bit) of the ADC command - see Section ,
Result
Queue
System
Memory
RFIFOn
ADC
Decoder
(16-bits)
(16-bits)
FIFO
Control
Unit
eQADC SSI
eQADC
ADC
eQADC SSI
External Device
Logic
&
Buffers
DMA
Transaction
Done Signals
Host CPU
or
DMAC
DMA
or Interrupt
Requests
NOTES:
n = 0, 1, 2, 3, 4, 5
ADC Result
RFIFO Header
Result
Message
Result
Format
&
Calibration
Submodule
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