Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5566 Microcontroller Reference Manual, Rev. 2
19-44 Freescale Semiconductor
header to determine the RFIFO to which the ADC result should be sent. After in an RFIFO, the ADC result
is moved to the corresponding user result queue by the host CPU or by the eDMA as they respond to
interrupt and eDMA requests generated by the eQADC. The eQADC generates these requests whenever
an RFIFO has at least one entry.
NOTE
While conversion results are returned, the eQADC is checking the number
of entries in the RFIFO and generating requests to empty it. The process of
pushing and popping ADC results to and from an RFIFO can occur
simultaneously.
Figure 19-24. Command Flow During eQADC Operation
Command
Queue
System
Memory
CFIFOn
ADC
Priority
Command
Buffer
(32-bits)
(32-bits)
FIFO
Control
Unit
To
ADCs
eQADC SSI
eQADC
ADC
eQADC SSI
External Device
Logic
&
Buffers
DMA
Transaction
Done Signals
Host CPU
or
DMAC
DMA
or Interrupt
Requests
NOTES:
n = 0, 1, 2, 3, 4, 5
ADC Command
CFIFO Header
Command
Message
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