NXP Semiconductors MPC5566 - Bus Transfers Initiated by an External Master

External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 12-61
Table 12-25 shows the 3-bit values that indicate slaves in the MCU, as well as the resulting upper 12
address bits required to appropriately match up with the memory map of each internal slave.
12.4.2.10.2 Bus Transfers Initiated by an External Master
The external master gets ownership of the bus (see Section 12.4.2.8, “Arbitration”) and asserts TS to
initiate an external master access. The access is directed to the internal bus only if the input address
matches to the internal address space. The access is terminated with either TA or TEA. If the access was
successfully completed, the MCU asserts TA, and the external master can proceed with another external
master access, or relinquish the bus. If an address or data error was detected internally, the MCU asserts
TEA for one clock.
Table 12-25. EBI Internal Slave Address Decoding
Internal Slave External ADDR[8:11]
1
1
Value on upper 4 bits of 24-bit external address bus ADDR[8:31]. ADDR[8] determines whether the access is on
or off chip.
Internal Addr[0:7]
2
2
Value on upper 8 bits of 32-bit internal address bus.
Internal Addr[8:11]
3
3
Value on bits 8:11 of 32-bit internal address bus.
(off-chip) 0b0xxx — —
Internal flash 0b10xx 0b0000_0000 0b00, ADDR[10:11]
Internal SRAM 0b1100 0b0100_0000 0b0000
Reserved 0b1101 0b0110_0000 0b0000
Bridge A peripherals 0b1110 0b1100_0011 0b1111
Bridge B peripherals 0b1111 0b1111_1111 0b1111