Enhanced Direct Memory Access (eDMA)
MPC5566 Microcontroller Reference Manual, Rev. 2
9-14 Freescale Semiconductor
complete, disabling the DMA hardware request. Otherwise if the D_REQ bit is cleared, the state of the
EDMA_ERQR bit is unaffected.
9.2.2.4 eDMA Enable Error Interrupt Registers (EDMA_EEIRH, EDMA_EEIRL)
The EDMA_EEIRH and EDMA_EEIRL provide a bit map for the 64 channels to enable the error interrupt
signal for each channel.EDMA_EEIRH supports channels 63–32, while EDMA_EEIRL covers channels
31–0.
The state of any given channel’s error interrupt enable is directly affected by writes to these registers; it is
also affected by writes to the EDMA_SEEIR and EDMA_CEEIR. The EDMA_SEEIR and
EDMA_CEEIR are provided so that the error interrupt enable for a single channel can easily be modified
without the need to perform a read-modify-write sequence to the EDMA_EEIRH and EDMA_EEIRL.
Both the DMA error indicator and this error interrupt enable flag must be asserted before an error interrupt
request for a given channel is asserted.
Address: Base + 0x0010 Access: User read/write
0123456789101112131415
R
EEI
63
EEI
62
EEI
61
EEI
60
EEI
59
EEI
58
EEI
57
EEI
56
EEI
55
EEI
54
EEI
53
EEI
52
EEI
51
EEI
50
EEI
49
EEI
48
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
EEI
47
EEI
46
EEI
45
EEI
44
EEI
43
EEI
42
EEI
41
EEI
40
EEI
39
EEI
38
EEI
37
EEI
36
EEI
35
EEI
34
EEI
33
EEI
32
W
Reset0000000000000000
Figure 9-6. eDMA Enable Error Interrupt High Register (EDMA_EEIRH)
Address: Base + 0x0014 Access: User R/W
0123456789101112131415
R
EEI
31
EEI
30
EEI
29
EEI
28
EEI
27
EEI
26
EEI
25
EEI
24
EEI
23
EEI
22
EEI
21
EEI
20
EEI
19
EEI
18
EEI
17
EEI
16
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
EEI
15
EEI
14
EEI
13
EEI
12
EEI
11
EEI
10
EEI
09
EEI
08
EEI
07
EEI
06
EEI
05
EEI
04
EEI
03
EEI
02
EEI
01
EEI
00
W
Reset0000000000000000
Figure 9-7. eDMA Enable Error Interrupt Low Register (EDMA_EEIRL)
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