Enhanced Serial Communication Interface (eSCI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 21-33
21.4.8.2 Disabling the eSCI
The module disable bit (ESCIx_CR2[MDIS]) in the eSCI control register 2 can be used to turn off the
eSCI. This saves power by stopping the eSCI core from being clocked. By default the eSCI is enabled
(ESCIx_CR2[MDIS]=0).
21.4.9 Interrupt Operation
Only the eSCI originates interrupt requests. The following sections describe how the eSCI generates a
request and how the MCU acknowledges that request. The eSCI only has a single interrupt line (eSCI
interrupt signal, active high operation) and all the following interrupts, when generated, are ORed together
and issued through that port.
21.4.9.1 Interrupt Sources
There are several interrupt sources that can generate an eSCI interrupt to the CPU. They are listed with
details and descriptions in Table 21-21.
Table 21-21. eSCI Interrupt Flags, Sources, Mask Bits, and Descriptions
Interrupt
Source
Flag Description Source
Local
Enable
Transmitter TDRE Indicates that a byte was transferred from ESCIx_DR to the transmit
shift register. The transmit data register empty (TDRE) interrupt is set
high by the eSCI when the transmit shift register receives data, 8 or 9
bits, from the eSCI data register, ESCIx_DR. A TDRE interrupt
indicates that the transmit data register (ESCIx_DR) is empty and that
a new data can be written to the ESCIx_DR for transmission. The
TDRE bit is cleared by writing a one to the TDRE bit location in the
ESCIx_SR.
ESCIx_SR[0] TIE
Transmitter TC Indicates that a transmit is complete. The transmit complete (TC)
interrupt is set by the eSCI when a transmission has completed. A TC
interrupt indicates that there is no transmission in progress. TC is set
high when the TDRE flag is set and no data, preamble, or break
character is being transmitted. When TC is set, the TXD pin becomes
idle (logic 1). The TC bit is cleared by writing a one to the TC bit
location in the ESCIx_SR.
ESCIx_SR[1] TCIE
Receiver RDRF Indicates that received data is available in the eSCI data register. The
receive data register full (RDRF) interrupt is set when the data in the
receive shift register transfers to the eSCI data register. An RDRF
interrupt indicates that the received data has been transferred to the
eSCI data register and that the received data can now be read by the
MCU. The RDRF bit is cleared by writing a one to the RDRF bit
location in the ESCIx_SR.
ESCIx_SR[2] RIE
Receiver IDLE Indicates that receiver input has become idle. The idle line (IDLE)
interrupt is set when 10 consecutive logic 1s (if M = 0) or 11
consecutive logic 1s (if M = 1) appear on the receiver input. After the
IDLE is cleared, a valid frame must again set the RDRF flag before an
idle condition can set the IDLE flag.
The IDLE bit is cleared by writing
a one to the IDLE bit location in the ESCIx_SR.
ESCIx_SR[3] ILIE
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