Deserial Serial Peripheral Interface (DSPI)
MPC5566 Microcontroller Reference Manual, Rev. 2
20-42 Freescale Semiconductor
20.4.4.4 DSI Deserialization
When all bits in a DSI frame have been shifted in, the frame is copied to the DSPIx_DDR. This register
presents the deserialized data as parallel output signal values. The DSPIx_DDR is memory mapped to
allow host software to read the deserialized data directly. Figure 20-20 shows the DSI deserialization logic.
for more information on the DSPIx_DDR.
See Section 20.3.2.14, “DSPI DSI Deserialization Data Register (DSPIx_DDR).”
Figure 20-20. DSI Deserialization Diagram
20.4.4.5 DSI Transfer Initiation Control
Data transfers for a master DSPI in DSI configuration are initiated by a condition. When chaining DSPIs,
the master and all slaves must be configured for the transfer initiation. The transfer initiation conditions
are selected by the TRRE and CID bits in the DSPIx_DSICR.
Table 20-18 lists the four transfer initiation conditions.
20.4.4.5.1 Continuous Control
For continuous control, the initiation of a transfer is based on the baud rate at which data is transferred
between the DSPI and the external device. The baud rate is set in the DSPIx_CTAR selected by the
DSICTAS field in the DSPIx_DSICR. A new DSI frame shifts out when the previous transfer cycle has
completed and the delay after transfer (t
DT
) has elapsed.
Table 20-18. DSI Data Transfer Initiation Control
DSPIx_DSICR Bits
Type of Transfer Initiation Control
TRRE CID
0 0 Continuous
0 1 Change in data
1 0 Triggered
1 1 Triggered or change in data
SIN
Control
logic
0 1 • • • • • 15
Shift register
16
Slave bus interface
ParallelDSI deserialization
data register
outputs
16
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