Enhanced Serial Communication Interface (eSCI)
MPC5566 Microcontroller Reference Manual, Rev. 2
21-36 Freescale Semiconductor
The eSCI settings must be made according to the LIN specification. The eSCI must be configured for
2-wire operation (2 wires connected to the LIN transceiver) with 8 data bytes and no parity. Normally a
13-bit break is used, but the eSCI can also be configured for 10-bit breaks as required by the application.
21.4.10.1 Features of the LIN Hardware
The eSCI’s LIN hardware has several features to support different revisions of the LIN slaves. The
ESCIx_LTR can be configured to include or not include header bits in the checksum on a frame by frame
basis. This feature supports LIN slaves with different LIN revisions. The LIN control register allows the
application to automatically calculate the parity bits in the ID field and insert double stop flags a bit error.
The BRK13 bit in ESCIx_CR2 decides whether to generate 10 or 13 bit break characters.
NOTE
LIN 2.0 requires a 13-bit break character. Set the BRK13 bit to 1. The eSCI
bus works when BRK13 = 0, but the setting does not comply with LIN 2.0.
The application software can disable checksum generation/verification for individual frames to perform
the functions externally and use the LIN hardware to append two CRC bytes (Figure 21-24). Although the
LIN standard does not include CRCs, CRCs are processed as data bytes by the LIN protocol. CRCs are
used in software applications that process very large frames. The eSCI and FlexCAN modules use the same
CRC polynomial, the LIN protocol processes CAN bytes as data bytes.
Figure 21-24. LIN Frame with CRC bytes
To force a resync of the LIN FSM, use the LRES bit in the LIN control register. Typically LIN hardware
automatically discards the frame when a bit error is detected.
21.4.10.2 Generating a TX Frame
The following procedure describes how a basic TX frame is generated.
The frame is controlled via the LIN transmit register (ESCIx_LTR). Initially, the application software must
check the TXRDY bit (either using an interrupt, the TX DMA interface, or by polling the LIN status
register). If TXRDY is set, the register is writable. Before each write, TXRDY must be checked (though
this step is performed automatically in DMA mode). The first write to the ESCIx_LTR must contain the
LIN ID field. The next write to ESCIx_LTR specifies the length of the frame (0 to 255 Bytes). The third
write to ESCIx_LTR contains the control byte (frame direction, checksum/CRC settings). Note that
timeout bits are not included in TX frames, since they only refer to LIN slaves. The three previously
mentioned writes to the ESCIx_LTR specify the LIN frame data. After the LIN frame data is specified, the
eSCI LIN hardware starts to generate a LIN frame.
First, the eSCI transmits a break field. The sync field is transmitted next. The third field is the ID field.
After these three fields have been broadcast, the ESCIx_LTR accepts data bytes; the LIN hardware
transmits these data bytes as soon as they are available and can be sent out. After the last step the LIN
hardware automatically appends the checksum field.
Break Sync ID Data Data CRC1 CRC2 CSum• • •
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