Enhanced Time Processing Unit (eTPU)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 18-11
18.2.1 User Configuration Mode
By having access to the shared code memory (SCM), the core has the ability to program the eTPU cores
with time functions.
18.2.2 User Mode
In user mode the core does not access the eTPU shared code memory, and pre-defined eTPU functions are
used.
18.2.3 Debug Mode
The core debugs eTPU code, accessing special trace/debug features via Nexus interface:
— Hardware breakpoint/watchpoint setting
— Access to internal registers
— Single-step execution
— Forced instruction execution
— Software breakpoint insertion and removal
18.2.4 Module Disable Mode
eTPU engine clocks are stopped through a register write to ETPU_ECR bit MDIS, saving power. Input
sampling stops. eTPU engines can be in stop mode independently. Module disable mode stops only the
engine clock, so that the shared BIU and global channel registers can be accessed, and interrupts and DMA
requests can be cleared and enabled/disabled. An engine only enters module disable mode when any
currently running thread is finished.
These modes are loosely selected: there is no unique register field or signals to choose between them.
Some features of one mode can be used with features of other modes.
18.2.5 eTPU Mode Selection
User and user configuration are the production operating modes, and differ from each other only in access
to SCM.
Module disable mode is entered by setting ETPU_ECR[MDIS]. eTPU engines can be individually stopped
(there is one ETPU_ECR for each engine).
18.3 External Signal Description
18.3.1 Overview
There are a total 65 external signals in each eTPU engine:
• 32 channel input signals
• 32 channel output signals
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