NXP Semiconductors MPC5566 - Interrupts and DMA Requests

Deserial Serial Peripheral Interface (DSPI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 20-65
20.4.9 Interrupts and DMA Requests
The DSPI has five conditions that can generate interrupt requests only, and two conditions that can
generate interrupt or DMA requests. Table 20-30 lists the conditions that can generate a DMA request or
interrupt request.
Each condition has a flag bit and a request enable bit. The flag bits are described in the Section 20.3.2.4,
“DSPI Status Register (DSPIx_SR)” and the request enable bits are described in the Section 20.3.2.5,
“DSPI DMA / Interrupt Request Select and Enable Register (DSPIx_RSER).” The TX FIFO fill flag
(TFFF) and RX FIFO drain flag (RFDF) generate interrupt requests or DMA requests depending on the
TFFF_DIRS and RFDF_DIRS bits in the DSPIx_RSER.
20.4.9.1 End-of-Queue Interrupt Request (EOQF)
The end of queue equest indicates that the end of a transmit queue is reached. The end of queue request is
generated when the EOQ bit in the executing SPI command is asserted and the EOQF_RE bit in the
DSPIx_RSER is set. See the EOQ bit description in Section 20.3.2.4, “DSPI Status Register (DSPIx_SR).”
See Figure 20-34 and Figure 20-35 that illustrate when EOQF is set.
20.4.9.2 Transmit FIFO Fill Interrupt or DMA Request (TFFF)
The transmit FIFO fill request indicates that the TX FIFO is not full. The transmit FIFO fill request is
generated when the number of entries in the TX FIFO is less than the maximum number of possible entries,
and the TFFF_RE bit in the DSPIx_RSER is set. The TFFF_DIRS bit in the DSPIx_RSER selects whether
a DMA request or an interrupt request is generated.
20.4.9.3 Transfer Complete Interrupt Request (TCF)
The transfer complete request indicates the end of the transfer of a serial frame. The transfer complete
request is generated at the end of each frame transfer when the TCF_RE bit is set in the DSPIx_RSER. See
the TCF bit description in Section 20.3.2.4, “DSPI Status Register (DSPIx_SR).” See Figure 20-34 and
Figure 20-35 that illustrate when TCF is set.
Table 20-30. Interrupt and DMA Request Conditions
Condition Flag Interrupt DMA
End of transfer queue has been reached (EOQ) EOQF X
TX FIFO is not full TFFF X X
Current frame transfer is complete TCF X
TX FIFO underflow has occurred TFUF X
RX FIFO is not empty RFDF X X
RX FIFO overflow occurred RFOF X
A FIFO overrun occurred
1
1
The FIFO overrun condition is created by ORing the TFUF and RFOF flags together.
TFUF ORed with RFOF X