e200z6 Core Complex
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 3-3
3.1.2 Overview
The e200z6 core integrates an integer execution unit, branch control unit, instruction fetch and load/store
units, and a multi-ported register file capable of sustaining three read and two write operations per clock.
Most integer instructions execute in a single-clock cycle. Branch target prefetching is performed by the
branch target address cache to allow single-cycle branches in many cases.
The e200z6 core complex is built on a single-issue, 32-bit Power Architecture design with 64-bit
general-purpose registers (GPRs). Power Architecture floating-point instructions are not supported in
hardware, but are trapped and may be emulated by software. A signal processing extension (SPE) auxiliary
processing unit (APU) is provided to support real-time fixed point and single-precision floating point
operations using the general-purpose registers. All arithmetic instructions that execute in the core operate
on data in the GPRs. The registers have been extended to 64-bits to support vector instructions defined by
the SPE APU. These instructions operate on 16-bit or 32-bit data types, and produce vector or scalar
results.
In addition to the base Power Architecture instruction set, the e200z6 core also implements the VLE
(Variable Length Encoding) APU, providing improved code density.
3.1.3 Features
The following is a list of some key features of the e200z6:
• Single issue, 32-bit CPU built on the Power Architecture embedded category
• Implements the VLE APU for reduced code footprint. Refer to EREF: A Programmer's Reference
Manual for Freescale Book E Processors and to VLEPIM: Variable Length Encoding (VLE)
Extension Programming Interface Manual.
• In-order execution and retirement
• Precise exception handling
• Branch target address cache
— Dedicated branch address calculation adder
— Branch target prefetching
— Branch lookahead buffers of depth 2
• Load/store unit: Pipelined operation supports throughput of one load or store operation per cycle
• 64-bit general-purpose register file
• Memory management unit (MMU) with 32-entry fully-associative TLB and multiple page size
support
• 32 KB, 4- or 8-way set associative unified cache
— Cache is configurable by software
— Minimize power use by the cache by selecting CORG = 1 or by setting WAM = 1.
Refer to Table 3-9.
• Periodic timer and watchdog functions
• Periodic system integrity can be monitored through parallel signature checks
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