NXP Semiconductors MPC5566 - DSPI Baud Rate and Clock Delay Generation

Deserial Serial Peripheral Interface (DSPI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 20-53
20.4.6 DSPI Baud Rate and Clock Delay Generation
The SCKx frequency and the delay values for serial transfer are generated by dividing the system clock
frequency by a prescaler and a scaler with the option of doubling the baud rate.
Figure 20-32 shows conceptually how the SCK signal is generated.
Figure 20-32. Communications Clock Prescalers and Scalers
20.4.6.1 Baud Rate Generator
The baud rate is the frequency of the serial communication clock (SCKx). The system clock is divided by
a baud rate prescaler (defined by DSPIx_CTAR[PBR]) and baud rate scaler (defined by
DSPIx_CTAR[BR]) to produce SCKx with the possibility of doubling the baud rate. The DBR, PBR, and
BR fields in the DSPIx_CTARs select the frequency of SCKx using the following formula:
Table 20-23 shows an example of a computed baud rate.
20.4.6.2 PCS to SCK Delay (t
CSC
)
The PCSx to SCKx delay is the length of time from assertion of the PCSx signal to the first SCKx edge.
See Figure 20-34 for an illustration of the PCSx to SCKx delay. The PCSSCK and CSSCK fields in the
DSPIx_CTARn registers select the PCSx to SCKx delay, and the relationship is expressed by the following
formula:
Table 20-24 shows an example of the computed PCS to SCK delay.
Table 20-23. Baud Rate Computation Example
f
SYS
PBR
Prescaler
Value
BR
Scaler
Value
DBR
Value
Baud Rate
100 MHz 0b00 2 0b0000 2 0 25 Mb/sec
20 MHz 0b00 2 0b0000 2 1 10 Mb/sec
Table 20-24. PCS to SCK Delay Computation Example
PCSSCK
Prescaler
Value
CSSCK
Scaler
Value
f
SYS
PCS to SCK Delay
0b01 3 0b0100 32 100 MHz 0.96 μs
Prescaler
1
Scaler
1 + DBR
System clock SCKx
SCK baud rate
f
SYS
PBRPrescalerValue
----------------------------------------------------------
1DBR+
BRScalerValue
--------------------------------------------
×=
t
CSC
=
f
SYS
CSSCK
×
PCSSCK
1
×