NXP Semiconductors MPC5566 - Overrun Status Register (SIU_OSR)

System Integration Unit (SIU)
MPC5566 Microcontroller Reference Manual, Rev. 2
6-18 Freescale Semiconductor
6.3.1.7 Overrun Status Register (SIU_OSR)
The SIU_OSR flag bits indicate that an overrun has occurred.
The following table describes the fields in the overrun status register:
Address: Base + 0x0020 Access: R/W
0123456789101112131415
R0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
OVF
15
OVF
14
OVF
13
OVF
12
OVF
11
OVF
10
OVF
9
OVF
8
OVF
7
OVF
6
OVF
5
OVF
4
OVF
3
OVF
2
OVF
1
OVF
0
W
Reset0000000000000000
Figure 6-8. Overrun Status Register (SIU_OSR)
Table 6-14. SIU_OSR Field Descriptions
Field Description
0–15 Reserved
16–31
OVFn
Overrun flag n. This bit is set when an overrun occurs on IRQ[n]. Bit 31 (OVF0) is the overrun flag for IRQ[0]; bit 16
(OVF15) is overrun flag for IRQ[15].
0 No overrun occurred.
1 An overrun occurred.