System Integration Unit (SIU)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 6-121
6.4.2 Reset Control
The reset controller logic is located in the SIU. Refer to Section 6.2.1.1, “Reset Input (RESET),” and
Section 6.2.1.2, “Reset Output (RSTOUT)” for details on the reset operations.
6.4.2.1 RESET Pin Glitch Detect
The reset controller provides a glitch detect feature on the RESET pin. If the reset controller detects that
the RESET pin is asserted for more than two clock cycles, the event is latched. After the latch is set, if the
RESET pin is negated before 10 clock cycles is reached, the reset controller sets the RGF bit without
affecting any of the other bits in the reset status register (SIU_RSR). The latch is cleared when the RGF
bit is set or a valid reset is recognized. The RGF bit remains set until cleared by a software or the RESET
signal asserts for 10 clock cycles. The reset controller does not respond to assertions of the RESET pin if
a reset cycle is already being processed.
6.4.3 External Interrupt
There are 1516 external interrupt inputs IRQ[0]–IRQ[15] to the SIU. The IRQ inputs can be configured
for rising-edge events, falling-edge events, or both. Each IRQ input has a flag bit in the external interrupt
status register (SIU_EISR). The flag bits for the IRQ[4:15] inputs are OR’ed together to form one interrupt
request to the interrupt controller (OR function performed in the integration glue logic). The flag bits for
the IRQ[0:3] inputs can generate either an interrupt request to the interrupt controller or a DMA transfer
request to the DMA controller.
Figure 6-170 shows the DMA and interrupt request connections to the interrupt and DMA controllers.
The SIU contains an overrun request for each IRQ and one combined overrun request which is the logical
OR of the individual overrun requests. Only the combined overrun request is used in the device, and the
individual overrun requests are not connected.
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