NXP Semiconductors MPC5566 - Emios Channel Counter Register (Emios_Ccntrn)

Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 17-13
17.3.1.6 eMIOS Channel Counter Register (EMIOS_CCNTRn)
The EMIOS_CCNTRn contains the value of the internal counter. When GPIO mode is selected or the
channel is frozen, the EMIOS_CCNTRn is readable and writable. For all others modes, the
EMIOS_CCNTRn is a read-only register. When entering some operating modes, this register is
automatically cleared.
Refer to Section 17.4.4.4, “Unified Channel Operating Modes,” for details.
17.3.1.7 eMIOS Channel Control Register (EMIOS_CCRn)
The eMIOS_CCRn enables the setting of several control parameters for a unified channel. Among these
controls are the setting of a channel prescaler, channel mode selection, input trigger sensitivity and
filtering, interrupt and DMA request enabling, and output mode control.
Address: UCn Base + 0x0008 Access: R/O
0123456789101112131415
R00000000 C
W
1
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RC
W
1
Reset0000000000000000
1
In GPIO mode or freeze action, this register is writable.
Figure 17-7. eMIOS Channel Counter Register (EMIOS_CCNTRn)
Address: UCn Base + 0x000C Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
FREN ODIS ODISSL UCPRE
UCP
REN
DMA
0
IF FCK FEN
0
W
1
Reset000 0000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R000 00
BSL EDSEL EDPOL MODE
W
1
FORCMA FORCMB
Reset000 0000000000000
Figure 17-8. eMIOS Channel Control Register (EMIOS_CCRn)